1. Field of the Invention
The present invention relates to digital signal processing and, more particularly, to methods and apparatus that utilize noise shaping technology for DC offset cancellation prior to digital demodulation.
2. Description of the Related Art
Referring to FIG. 1, a block diagram of a satellite QPSK (Quadrature Phase Shift Keying) receiver is schematically illustrated. In FIG. 1, an antenna 1 is provided to detect a radio frequency (RF) signal, typically in Ku band, which is then converted by a LNB low-noise block (not shown in the drawing) into an intermediate frequency signal IF_1, generally ranging from about 950 MHz to about 1450 MHz in frequency. A tuner 2 receives the signal IF_1 and transmits another intermediate frequency signal IF_2, typically at about 479.5 MHz, to scalars 3 and 4. A local oscillator 5 transmits a local oscillating signal (LO) to scalars 3 and 4. As shown, the local oscillating signal LO transmitted to scalar 4 is shifted by 90 degrees in phase from the local oscillating signal LO transmitted to scalar 3. The scalars 3 and 4 mix the signal IF_2 with the respective local oscillating signal LO, thus generating analog in-phase signal I.sub.A and analog quadrature phase signal Q.sub.A, respectively.
An analog-to-digital converter (ADC) 7 is utilized to digitize the analog in-phase signal I.sub.A, thus providing a digital in-phase signal I.sub.D, while an ADC 8 digitizes the analog quadrature phase signal Q.sub.A to provide a digital quadrature phase signal Q.sub.D. Both the digital in-phase signal I.sub.D and the digital quadrature phase signal Q.sub.D are transmitted to a digital demodulator 10 for further processing. Preferably, ADCs 7 and 8 have 6-bit resolution. Moreover, a clock generator 9 generates a fixed-frequency clock signal CLK, preferably with a frequency greater than 60 MHz, for driving ADCs 7 and 8.
Since DC offset in a QPSK signal can result in problems during demodulation, it is preferable to eliminate any DC offset prior to the signal entering digital demodulator 10. Circuits for DC offset cancellation can be categorized into three types: analog, semi-analog, and digital.
The analog type circuit for DC offset cancellation is employed to eliminate DC offset from analog signals. When applied to a satellite QPSK receiver, as shown in FIG. 1, analog type circuits should be arranged between scalars 3 and 4 and the associated ADC 7 or 8, in order to process I.sub.A and Q.sub.A, respectively. U.S. Pat. No. 5,508,656 discloses an example of an analog type circuit for DC offset cancellation. This patent utilizes a switching-capacitor technique for DC offset cancellation.
U.S. Pat. Nos. 5,617,060 and 5,699,011 disclose examples of a semi-analog type circuit for DC offset cancellation. When applied to a satellite QPSK receiver, such as depicted in FIG. 1, semi-analog type circuits are used to process both the I and Q channel, and are arranged in feedback loops from I.sub.D to I.sub.A and from Q.sub.D to Q.sub.A, respectively. In these systems, the respective digital signal, I.sub.D or Q.sub.D, is processed to acquire its digital DC offset, after which a digital-to-analog converter (DAC) converts the digital DC offset to analog, and feeds the analog DC offset back for subtraction from the respective analog signal, I.sub.A or Q.sub.A.
A digital type circuit for DC offset cancellation is disclosed in U.S. Pat. No. 5,281,968, and is employed to cancel DC offsets from digital signals. When applied to a satellite QPSK receiver, such as depicted in FIG. 1, a digital type circuit should be arranged between both ADC 7 and digital demodulator 10 and ADC 8 and digital demodulator 10. These circuits are used to process I.sub.D and Q.sub.D, respectively, to eliminate any DC offset contained therein.
FIG. 2 provides a block diagram of a conventional digital type circuit for DC offset cancellation. The circuit comprises a subtracter 20, an attenuator 21 and an accumulator 22. As shown in FIG. 2, subtracter 20 receives the respective digital signal, I.sub.D or Q.sub.D, which is designated by digital signal x, from the associated ADC 7 or ADC 8, and subtracts a signal Vdc, representing the DC offset, from signal x, thus generating output signal y. Signal y is then fed back to accumulator 22 to generate accumulation value z, which is sent to attenuator 21. In FIG. 2, accumulator 22 consists of a delay 23, which is expressed in the form of a Z-transform, and an adder 24. In accumulator 22, the output of adder 24 is registered and delayed for a sampling period by delay 23, after which it is fed back to adder 24, which adds it to current signal y. Attenuator 21 is used to multiply the accumulation value z by a constant k, which is typically a very small negative power of two such as 2.sup.-16, to generate DC offset signal Vdc. DC offset signal Vdc is then subtracted from digital signal x in subtracter 20 to generate output signal y. Output signal y is then transmitted to digital demodulator 10 for further processing. Thus, any DC offset is canceled from I.sub.D or Q.sub.D, respectively, before being sent to digital demodulator 10.
Disadvantageously, application of the circuit of FIG. 2 to a satellite QPSK receiver gives rise to an enormous increase in the required word length for QPSK signals. For ease and clarity, assume that ADC 7 and ADC 8 are provided with 6-bit resolution and their outputs are in 2's-complement form. This six-bit format can be used to express an integer ranging from -32 to 31 in decimal notation with the least significant bit representing one. To practically cancel DC offset signal Vdc, signal y should be represented by a large number of fraction bits in addition to the integer bits. For example: ##EQU1##
In other words, the conventional circuit of FIG. 2 requires the corrected digital in-phase signal I.sub.D and the corrected digital quadrature phase signal Q.sub.D to have a very large word length. In general, the larger the over sampling rate, the ratio of the ADC sample rate to the QPSK symbol rate, the larger the required word length. In the application of single channel per carrier (SCPC), the over sampling rate is quite large and very large word length is needed. Thus, these greater word lengths expand the hardware complexity of the arithmetic circuits of demodulator 10 operating on the QPSK signals. Furthermore, because the frequency of the clock signal CLK is usually greater than 60 MHz, the demodulator may not have sufficient time to process the QPSK signals with greater word length.